/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
 * Copyright (C) 2016-2018, LomboTech Co.Ltd.
 * Author: lomboswer <lomboswer@lombotech.com>
 *
 * Lombo VISS-VIC controller register definitions header
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 */

#ifndef ___VISS_VIC___H___
#define ___VISS_VIC___H___

/******************************************************************************
 * base operations
 *****************************************************************************/

void csp_vic_set_register_base(void *base);

/**
 * VIC enable
 */
u32 csp_vic_enable(void);

/**
 * VIC disable
 */
u32 csp_vic_disable(void);

/**
 * VIC EAV or SAV checkout error ints enable
 */
u32 csp_vic_ints_enable(void);


/**
 * VIC EAV or SAV checkout error ints disable
 */
u32 csp_vic_ints_disable(void);


/**
 * VIC EAV or SAV checkout error ints pending status
 */
void csp_vic_clear_pd(void);


/**
 * VIC EAV or SAV checkout error ints pending status
 */
u32 csp_vic_get_int_pd(void);


/**
 * VIC status
 */
u32 csp_vic_status(void);

/******************************************************************************
 * interface configure
 *****************************************************************************/

/**
 * Select VIC data path
 */
u32 csp_vic_data_path(u32 path);

/**
 * Set PCLK polarity
 */
u32 csp_vic_set_pclk_polarity(u32 pol);

/**
 * Set Filed polarity
 */
u32 csp_vic_set_field_polarity(u32 pol);

/**
 * Set HSYNC polarity
 */
u32 csp_vic_set_hsync_polarity(u32 pol);

/**
 * Set VSYNC polarity
 */
u32 csp_vic_set_vsync_polarity(u32 pol);

/**
 * Set PCLK phase
 */
u32 csp_vic_set_pclk_phase(u32 phase);

/**
 * Select DVP data bus protocol
 */
u32 csp_vic_select_data_protocol(u32 ptcl);

/**
 * Select YUV componet sequence
 */
u32 csp_vic_set_yuv_seq(u32 seq);

/**
 * Select embedded SYNC code position for BT.1120 mode0, 16-bit data bus
 */
u32 csp_vic_select_sync_code_position(u32 pos);

/**
 * Select SYNC protocol
 */
u32 csp_vic_select_sync_protocol(u32 ptcl);

/**
 * Select Field signal detection
 */
u32 csp_vic_select_field_detecton(u32 det);

/**
 * Select input video mode
 */
u32 csp_vic_select_video_mode(u32 mode);

/**
 * Select sampling mode
 * @mode: PCLK_SM
 *	0: SDR
 *	1: DDR
 */
u32 csp_vic_select_pclk_sm(u32 mode);

/**
 * Set HSYNC front blanking offset, Only for BT.601 mode
 */
u32 csp_vic_hsync_fb_offset(u32 offset);

/**
 * Set HSYNC active width, Only for BT.601 mode
 */
u32 csp_vic_hsync_active_width(u32 width);

/**
 * Set Field1 vertical front blanking offset, Only for BT.601 mode
 */
u32 csp_vic_f1_vsync_fb_offset(u32 offset);

u32 csp_vic_set_channel_size(u32 x, u32 y);

/**
 * Set Field1 vertical active line, Only for BT.601 mode
 */
u32 csp_vic_f1_vsync_active_line(u32 line);

/**
 * Set Field1 vertical front blanking offset, Only for BT.601 mode
 */
u32 csp_vic_f2_vsync_fb_offset(u32 offset);

/**
 * Set Field2 vertical active line, Only for BT.601 mode
 */
u32 csp_vic_f2_vsync_active_line(u32 line);


void csp_vic_cfg_fifo(void);

/**
 * Reset VIC circuit
 */
u32 csp_vic_reset(void);


/**
 * csp_vic_chk_pd - check whether all the expected int pending have been raise
 */
void csp_vic_dump_regs(const char *func_name);

/**
 * enable vic output high 8bit data
 */
u32 csp_vic_output_high_8bit_data(u32 enable);

/**
 * enable vic output raw msb data
 */
u32 csp_vic_output_raw_msb_data(u32 enable);


#endif /* ___VISS_VIC___H___ */
